The invention concerns a method of frequency synthesis by means of a phase-locked loop, wherein a data-modulated output signal is generated by a voltage controlled oscillator (VCO) in the phase-locked loop in response to a modulating bit flow received on an input of the oscillator. Finally, the invention concerns a frequency synthesizing circuit as well as a radio telephone having such a circuit.
When data modulating the VCO in a PLL are constant (zeros or ones) for a period of some length or possess a majority of either zeros or ones, the output frequency of the VCO differs from the nominal centre frequency in this period owing to the modulation with data. The PLL therefore reacts by trying to bring the frequency back to the nominal centre frequency. This is a problem in particular in connection with telephones which are associated with digital cordless systems in which the VCO is modulated directly with data.
To obtain rapid locking, the loop must have a high loop bandwidth (about 20 kHz), while a low loop bandwidth (about 2 kHz) is required to prevent the modulation frequency from affecting the PLL. If the modulation in a data packet does not vary or possess a majority of either zeros or ones, the modulation frequency will be within the loop bandwidth.